Designing Pipeline FFT Processors using 3DIC Technology

Fast Fourier Transform (FFT) processing is an important component of many Digital Signal Processing systems. We focus on applications requiring large-point FFTs ( 1024), and where high-speed of operation has priority. We observe that the performance of pipelined large-point FFTs is limited due to the physical size and access times of the numerous First-in-First-out (FIFO) memories present in the design. We demonstrate the advantage of using 3D Integrated Circuit Technology to assist in memory banks interleaving and stacking, for boosting their performance. Our 3DIC design methodology involves commercial single-tier CAD tools with Perl, Python and TCL scripts to process their inputs and tie-up their single-tier outputs into a multi-tiered format. The design experiments utilize the 3-tier, 3- metal layer, fully depleted Silicon-on-Insulator 3D 0.18 m manufacturing process from MIT Lincoln Labs. A design for an 8192-pt. FFT with 24 bits fixed-point inputs (12-bits each of real and imaginary) is proposed which uses the Radix-2/4/8 Multi-path Delay Commutator Pipelined Architecture and which can operate at 214 Mhz to give a new FFT set every 19 s.